1. Field of the Invention
The present invention relates to a semiconductor integrated circuit and, more particularly, to a configuration for measuring an internal voltage generated internal to a semiconductor integrated circuit and for applying externally a voltage for estimation. More particularly, the invention relates to a configuration for estimating an internal voltage in a semiconductor memory device.
2. Description of the Background Art
In a semiconductor integrated circuit, a voltage at a desired voltage level is generated for reduction in number of pins, reduction in power consumption of a whole system, and others.
FIG. 23 is a diagram schematically showing the whole configuration of a nonvolatile semiconductor memory device as an example of such a semiconductor integrated circuit. In FIG. 23, a nonvolatile semiconductor memory device 900 includes: a memory array 901 having a plurality of nonvolatile memory cells arranged in rows and columns; an X decoder 902 for selecting a row in the memory array 901; a data register 903 for holding data of nonvolatile memory cells in one row in the memory array 901; an X address buffer 904 for buffering a received X address signal and supplying the buffered signal to the X decoder 902; a Y decoder 905 for decoding a received Y address signal and generating a column selection signal; and a Y gate 906 for selecting a register circuit included in the data register 903 in accordance with the column selection signal from the Y decoder 905.
In the data register 903, the register circuits are provided in correspondence with nonvolatile memory cells of one row in the memory array 901. At the time of writing, write data is sequentially stored in the register circuits in the data register 903. At the time of reading, data read from the nonvolatile memory cells in a selected row is held in the data register 903.
The nonvolatile semiconductor memory device 900 further includes: a data output buffer 910 and an address/data input buffer 911 which are coupled to a data/address terminal (pad) group 917; a write data input driver 908 for generating internal write data in accordance with write data applied from the address/data input buffer 911 and applying the internal write data to the Y gate 906 in a data writing operation mode; a Y address counter 907 for performing a counting operation with the Y address signal received from the address/data input buffer 911 being an initial value, sequentially shifting the Y address, and supplying a resultant Y address signal to the Y decoder 905; and a read data output amplifier 909 for amplifying read data selected by the Y gate 906 and applying resultant data to the data output buffer 910.
In the nonvolatile semiconductor memory device, data and an address are transferred via the data/address terminal group 917. In applying a command for instructing an operation mode, a command and an address signal are simultaneously supplied to a data terminal and an address terminal in the data/address terminal group 917. Thereafter, in writing data, write data is supplied to the data terminal in the data/address terminal group 917. FIG. 23 shows a case where 8-bit data DQ less than 7:0 greater than  is inputted and outputted as an example.
The nonvolatile semiconductor memory device 900 further includes: an OE buffer 919 for buffering an output enable signal OE applied via an input terminal (hereinafter, called a pad) 918 for application to the address/data input buffer 911 and a command decoder 912; a CE buffer 921 for buffering a chip enable signal CE supplied via a pad 920 for application to the address/data input buffer 911, the data output buffer 910, and the command decoder 912; a WE buffer 923 for buffering a write enable signal WE applied to the pad 920 for application to the command decoder 912; an RES buffer 925 for buffering a reset signal RES applied to a pad 924 for application to the signal to the command decoder 912; a buffer 927 for buffering a signal (external arbitrary signal other than the above signals) ETC for application to the command decoder 912; and an SC buffer 929 for buffering a shift clock signal SC applied to a pad 928 for application to the Y address counter 907.
An internal output enable signal from the OE buffer 919 is applied to the data output buffer 910. When the output enable signal OE is made active, the data output buffer 910 is activated and applies data received from the read data output amplifier 909 to the pad group 917. The chip enable signal CE attains an active state, to designate that the nonvolatile semiconductor memory device 900 is selected and a data access is performed. The data access means writing, reading and erasing operations. In accordance with the internal signals from the buffers 919, 921, 923, 925, and 927, the command decoder 912 decodes a command applied from the address/data input buffer 911 and generates an operation mode instruction signal instructing a designated operation mode.
The nonvolatile semiconductor memory device 900 further includes: a read/write/erase control circuit 913 for performing a control for executing the designated operation in response to the operation mode instruction signal from the command decoder 912; a reference voltage generating circuit 914 for generating reference voltages Vref1 and Vref2 at predetermined voltage levels under the control of the read/write/erase control circuit 913; a high voltage generating circuit 915 for generating positive high voltages VPP1 and VPP2 necessary for programming/erasing data under the control of the read/write/erase control circuit 913; and a high voltage generating circuit 916 for generating negative high voltages VNN1 and VNN2 under the control of the read/write/erase control circuit 913.
In FIG. 23, the high voltages VPP1, VPP2, VNN1 and VNN2 from the high voltage generating circuits 915 and 916 are shown being applied to the X decoder 902. The high voltages may be, however, transmitted to a bit line (memory cell column) via the Y gate 906 or may be applied to a substrate region in the memory array 901. The nonvolatile memory cell is constructed by a stack gate type field effect transistor having a floating gate and a control gate. Data is stored in accordance with an accumulation amount of charges in the floating gate.
At the time of injecting electrons to the floating gate, a positive high voltage is applied to the control gate, and a ground voltage or a negative high voltage is applied to the substrate region or drain region (bit line). In injecting electrons to the floating gate, channel hot electrons (CHE) injection or injection of electrons by an FN (Fouler-Nordheim) tunneling current is performed. The injection method differs according to the configuration of the nonvolatile semiconductor memory device. On the other hand, in the case of ejecting electrons from the floating gate of the nonvolatile memory cell, the negative high voltage or ground voltage is applied to the control gate, and the positive high voltage or ground voltage is applied to the drain or the substrate region. The voltage level of the high voltage to be used differs according to the operation modes. A high voltage at a necessary voltage level is generated from the high voltage generating circuits 915 and 916 for each of the operation modes.
Each of the high voltage generating circuits 915 and 916 determines the level of a high voltage to be generated, according to the reference voltages Vref1 and Vref2 from the reference voltage generating circuit 914. For example, such a adjusting scheme is employed that the high voltage VPP1 is voltage-divided and the divided voltage level is made equal to the level of the reference voltage Vref1. The high voltage generating circuit 915 determines the voltage level of the high voltage VPP1. For the negative high voltages VNN1 and VNN2, the voltage level is determined similarly. The negative voltage is level-sifted to be compared with the reference voltage, and the voltage levels of the negative high voltages VNN1 and VNN2 to be generated are set according to a comparison result, and accordingly, a necessary voltage is internally generated stably.
A power supply voltage VCC and a ground voltage VSS are applied externally to the nonvolatile semiconductor memory device 900. The reference voltage generating circuit 914 and the high voltage generating circuits 915 and 916 generate a reference voltage and a high voltage from the power supply voltage VCC and the ground voltage VSS.
The shift clock signal SC is applied upon writing/reading data. The Y address counter 907 sequentially increments or decrements the address from the initial value in accordance with the shift clock signal SC and supplies a resultant address to the Y decoder 905. That is, in accordance with the shift clock signal SC, writing/reading of data is executed externally of the memory device.
The voltage level of each of voltages from the reference voltage generating circuit 914 and the high voltage generating circuits 915 and 916 has to be accurately set. When each of the high voltages VPP (generically referring to VPP1 and VPP2) and VNN (generically referring to VNN1 and VNN2) is not at an accurate voltage level, programming/erasing is performed insufficiently. In order to monitor whether the reference voltage generating circuit 914 and the high voltage generating circuits 915 and 916 generate the internal voltages (reference voltage and positive and negative high voltages) at desired voltage levels at a test stage, pads PA1 to PA6 for monitoring are provided for the reference voltage generating circuit 914 and the high voltage generating circuits 915 and 916. Via the pads PA1 to PA6, the high voltages and the reference voltage are monitored externally and an internal circuit is operated forcedly by externally applying a voltage, with an external tester. The configuration of each of the sections will now be briefly described.
FIG. 24 is a diagram showing signals generated by the command decoder 912 and the read/write/erase control circuit 913 shown in FIG. 23. The command decoder 912 receives an 8-bit signal from a data input (DIN) buffer 911a included in the buffer 911 at an input node DATA less than 7:0 greater than , receives the write enable signal WE from the WE buffer 923 at an input node WEIN, and receives a reset signal from the RES buffer 925 at an input node RESIN. In response to the rising edge of the write enable signal WE, the command decoder 912 decodes the 8-bit signal applied from the DIN buffer 911a and activates an operation mode instruction signal corresponding to the designated operation mode in accordance with the decoding result. In FIG. 24, a reading mode instruction signal xcfx86RE, an erasing mode instruction signal xcfx86ER, and a programming mode instruction signal xcfx86PR are shown.
When the designated operation mode is completed, the write/read/erase control circuit 913 applies an operation completion instruction signal xcfx86CP to the command decoder 912 so that the command decoder 912 inactivates the operation mode instruction signal that is in the active state. In the write/read/erase control circuit 913, an operation of verifying whether or not data is accurately written in a memory cell is performed in writing data. The verifying operation is also executed under the control of the control circuit 913. Until the verifying operation is completed and memory cell data is accurately written in the selected memory cell, the operation completion instruction signal xcfx86CP is maintained in an inactive state.
The operations in writing data will now be briefly described with referring to a signal waveform diagram of FIG. 25. In writing data, a command xe2x80x9c10hxe2x80x9d instructing a writing mode is supplied to the DIN buffer 911a. When the write enable signal WE goes low to the L level, the command decoder 912 determines that a valid command is applied, decodes the command xe2x80x9c10hxe2x80x9d supplied from the DIN buffer 911a in response to the rising edge of the write enable signal WE, and sets the programming mode instruction signal xcfx86PR into an active state.
In response to the activation of the programming mode instruction signal xcfx86PR, the write/read/erase control circuit 913 causes the X address buffer 904 and the Y address counter 907 to accept an address from the address input buffer included in the address/data input buffer 911 from the next cycle. The Y address counter 907 performs a counting operation in accordance with the shift clock signal SC from the SC buffer 929 and sequentially changes the Y address from the initial value. The Y gate 906 is made conductive in accordance with the column selection signal from the Y decoder 905 and data is stored in the selected register circuit in the data register 903.
In the memory array 901, the X decoder 902 applies the high voltage VPP or VNN to a selected row in accordance with the high voltage VPP or VNN from the high voltage generating circuit 915 or 916. According to the method of programming data into the memory cell, a voltage corresponding to the write data is transmitted to each of bit lines. Which one of the positive high voltage VPP and negative high voltage VNN is applied to the X decoder 902 in the writing operation is determined according to the method of programming data to a memory cell. Here, in the writing operation, a memory cell is set into an erasure state or a programmed state in accordance with write data. When writing of necessary data is completed and all the data are accurately written, the write/read/erase control circuit 913 activates the operation completion instruction signal xcfx86CP. In response to the activation of the operation completion instruction signal xcfx86CP, the command decoder 912 makes the programming mode instruction signal xcfx86PR inactive.
Referring to FIG. 26, operations of the command decoder 912 and the write/read/erase control circuit 913 shown in FIG. 24 in the erasing mode will now be briefly described. The erasing mode is designated by supplying an erase command xe2x80x9c20hxe2x80x9d. At the rising edge of the write enable signal WE, the command decoder 912 decodes the erasure command and activates the erasing mode instruction signal xcfx86ER. In response to the activation of the erasing mode instruction signal xcfx86ER, the write/read/erase control circuit 913 performs an operation necessary for erasing data. According to whether the erasure is performed by injecting electrons into the floating gate or ejecting electrons from the floating gate, the high voltage generating circuits 915 and 916 generate the necessary high voltage(s) VPP and/or VNN. For example, when electrons are injected into the floating gate in the erasing operation, a positive high voltage is applied to the word line which is designated to be erased. When the application of erasing pulses and the erasing verifying operation are completed in erasing operation and erasure of data in the designated region is normally completed, then the write/read/erase control circuit 913 activates the operation completion instruction signal xcfx89CP. The command decoder 912 accordingly inactivates the erasing mode instruction signal xcfx86ER, to complete the erasing operation designated by the erasing command xe2x80x9c20hxe2x80x9d.
FIG. 27 is a diagram schematically showing the configuration of a section related to generation of a Y address. In accordance with a setting instruction signal xcfx86S from the control circuit 913, the Y address counter 907 takes in the Y address signal Y received from the address/data input buffer and is initialized to the Y address. The Y address counter 907 performs a counting operation synchronously with the rising edge of the shift clock signal SC applied from the SC buffer 929 and changes the value of output bits YAD less than 11:0 greater than  one by one. The Y decoder 905 decodes the count bits YAD less than 11:0 greater than  from the Y address counter 907 and supplies a column selection signal to the Y gate 905 in accordance with the decoding result. As shown in FIG. 28, the Y address counter 970 updates its counting value by one synchronously with the rising edge of the shift clock signal SC. In the selected row, therefore, columns are sequentially selected by the Y decoder 905. One row has 4K columns. Memory cells of eight bits are simultaneously selected by a single selecting operation of the Y gate 905. In each column address of the 4K column addresses, memory cells of eight bits (1 byte) are disposed. Therefore, one page has a size of 32 Kbits.
By generating the Y address signal internally in accordance with the shift clock signal SC, data can be written/read at high speed in accordance with, for example, a page mode.
FIG. 29 is a diagram schematically showing the configuration of an input buffer. Since the input buffer has the configuration similar to that of an input buffer which receives a chip select signal/CS, an input signal SIG is shown as a representative in FIG. 29. In FIG. 29, the input buffer includes: P-channel MOS transistors (insulated gate type field effect transistors) P0 and P1 which are connected in series between a power supply node 950 and an internal node 951; and N-channel MOS transistors N0 and N1 which are connected in parallel between the internal node 951 and ground node. The chip select signal /CS is applied to the gates of the MOS transistors P0 and N0, and the input signal SIG is applied to the gates of the MOS transistors P1 and N1 via the pad 940.
The chip select signal /CS is equivalent to the chip enable signal CE shown in FIG. 23, but is inverted in logic level. In an inactive state of the H level of the chip select signal /CS, the P-channel MOS transistor P0 is in an OFF state, and the N-channel MOS transistor N0 is in an ON state. In such a state, irrespective of the logic level of the input signal SIG, an internal signal IN from the internal node 951 is at the L level of the ground voltage VSS level. In the following, the chip select signal /CS is employed in place of the chip enable signal CE, but the implemented function is the same.
On the other hand, when the chip select signal /CS attains an active state at the L level, the MOS transistor P0 is turned on and the MOS transistor N0 is turned off. The MOS transistors P1 and N1 are coupled to the power supply node 950 via the MOS transistor P0, operate as a CMOS inverter, and generate the internal signal IN by inverting the input signal SIG applied to the pad 940. When the chip select signal /CS is in the active state at the L level, the internal signal is generated in accordance with an externally applied signal, and the nonvolatile semiconductor memory device can perform a designated operation.
FIG. 30 is a diagram showing an example of the configuration of the data output buffer. FIG. 30 shows one of the data output buffer circuits in the data output buffer 910 as a representative. In FIG. 30, the output buffer circuit includes: an inverter IV1 which receives an internal read data bit intQ; an inverter IV2 which receives an output enable signal /OE; an NAND circuit G1 which receives the internal read data bit intQ and an output signal of the inverter IV2; an NOR circuit G2 which receives an output signal of the inverter IV1 and the output enable signal /OE; a P-channel MOS transistor P2 which is made conductive, when the output signal of the NAND circuit G1 is at the L level, to transmit the power supply voltage VCC on a power supply node 955 to an output node 957; and an N-channel MOS transistor N2 which is made conductive, when the output signal of the NOR circuit G2 is at the H level, to drive the output node 957 to the ground voltage VSS level.
In reading data, a read command (for setting the chip select signal /CS to the L level and the write enable signal /WE to the H level) for instructing reading of data is supplied and the reading mode instruction signal xcfx86RE is responsively made active by the command decoder, so that a memory cell is selected and data is read internally. The output enable signal /OE is applied externally and controls the activation/inactivation of the data output buffer 910. When the output enable signal /OE is at the H level, an output signal of the NAND circuit G1 attains the high level, an output signal of the NOR circuit G2 attains the L level, both the MOS transistors P2 and N2 enter an OFF state, and the output buffer circuit enters an output high impedance state.
When the output enable signal /OE is set to the L level, the NAND circuit G1 and the NOR circuit G2 operate as an inverter. One of the MOS transistors P2 and N2 is turned on in accordance with the logic level of the internal read data bit intQ, and a data bit Q of the output node 957 is set to the H or L level, and data is read out externally.
FIG. 31A is a diagram showing voltages applied to the nodes at the time of injecting electrons to the floating gate in a nonvolatile memory cell. The memory cell includes: N-type impurity regions 962 and 964 formed at the surface of a P-type substrate 960; a floating gate 966 formed above a channel region between the impurity regions 962 and 964; and a control gate 968 formed above the floating gate 966. The impurity region 962 is connected to a source line S, and the impurity region 964 is connected to a bit line. The impurity regions 962 and 964 act as a source S and a drain D, respectively.
As shown in FIG. 31A, in the case of injecting electrons (e) from the substrate region 960 to the floating gate 966, a positive high voltage VPP is applied to the control gate 968. The impurity regions 962 and 964 are set in an electrically floating state. The substrate region 960 is set to the ground voltage or a negative voltage in accordance with the voltage level of the positive high voltage VPP. A voltage applied to the substrate region 960 is indicated by a reference character VN. Under this state, the electrons (e) flow in the form of Fowler-Nordheim (FN) tunneling current from the channel region in the substrate region 960 into the floating gate 966 and are accumulated in the floating gate 966. In this state, the threshold voltage of the memory cell increases. This state is referred to an erased or programmed state, according to the configuration of the memory cell array
On the other hand, in the case of ejecting electrons from the floating gate 966, as shown in FIG. 31B, the negative high voltage VNN is applied to the control gate 968 and the source is set to a floating state. The substrate region 960 is held at the ground voltage level. A positive voltage or ground voltage is applied to the impurity region 964 in accordance with the voltage level of the negative high voltage VNN. Under this state, the electrons flow from the floating gate 966 to the bit line (drain) via the impurity region 964 by the F-N tunneling current, so that the electrons are ejected from the floating gate 966. This state is a state where the threshold voltage is reduced and is called a programmed or erased state.
In the case of writing or erasing data, the high voltages VPP and VNN are applied in a pulse form. The pulse width is predetermined according to the voltage levels of the high voltages VPP and VNN. When the levels of the high voltages VPP and VNN are lower than a predetermined value, electrons are not sufficiently injected or ejected, so that the writing/erasing operation cannot be completed within a time period determined by a specification value. Usually, in the erasing/writing operation, a verifying operation is performed after completion of the erasing/writing operation. When the number of application times of the erasing/programming pulse reaches a predetermined number and the writing/erasing operation has not been completed yet, it is determined that an error occurs.
The voltage level of each of the high voltages VPP and VNN is determined by the reference voltage Vref (Vref1 and Vref2). In order to check whether the high voltages VPP and VNN and the reference voltage Vref are accurately generated internally at predetermined voltage levels, the pads PA1 to PA6 are provided in correspondence with the internal voltages VPP, VNN and Vref. In a test at a wafer level, a probe is applied to a pad of the pads PA1 to PA6 corresponding to the internal voltage to be estimated, and the levels of the internal voltages VPP, VNN, and Vref are monitored. A voltage is forcedly applied externally to each of the monitoring pads PA1 to PA6 to operate the internal circuits, whether the internal circuits operate normally or not is identified, and the characteristics of the internal circuits are estimated even in an internal voltage failure.
The pads PA1 to PA6 for monitoring are, however, used only for a test. When the nonvolatile semiconductor memory device is assembled in a package, the pads are not connected to external pin terminals. After the packaging, the levels of voltages generated internally are not conventionally tested.
When a failure occurs in a circuit which generates an internal voltage during the period from the completion of the test at the wafer level to the completion of packaging of the nonvolatile semiconductor memory device, a test of the internally generated voltages when a failure occurs at a chip level cannot be carried out.
When the voltages generated internally are measured externally and a voltage is forcedly applied externally, it is necessary to connect all the monitoring pads PA1 to PA6 to external pin terminals. When there are extra external pin terminals and free external pin terminals are present, by connecting the monitoring pads to the free external pin terminals, the internal voltages can be monitored externally and the internal voltages can be forcedly set externally. In this case, however, when the number of the free pin terminals is smaller than the number of the internal voltages to be tested, all of the internal voltages cannot be tested. In the case of adding further external pin terminals for the test of the internal voltages, the size of the package becomes larger and the cost becomes higher.
The problem related to the test of the internal voltages after the packaging is not generally limited to the nonvolatile semiconductor memory device. A similar problem occurs in a semiconductor integrated circuit such as a DRAM (Dynamic Random Access Memory), in which an internal voltage is generated from an external voltage.
It is an object of the present invention to provide a semiconductor integrated circuit allowing a test of an internal voltage without increasing the number of external pin terminals after packaging.
It is another object of the invention to provide a semiconductor integrated circuit allowing a test on a plurality of internal voltages by using a minimum required number of external pin terminals.
A semiconductor integrated circuit according to the invention includes: an internal voltage generating circuit for generating an internal voltage different in voltage level from first and second power supply voltages supplied externally; a buffer circuit coupled to a pad; and a switching circuit for inactivating the buffer circuit and coupling the internal voltage generating circuit to the pad in response to a control signal.
A semiconductor integrated circuit according to another aspect of the invention includes: an internal voltage generating circuit for generating an internal voltage different in voltage level from first and second power supply voltages; an internal voltage transmission line for transmitting the internal voltage; a switching circuit for isolating the internal voltage transmission line and the internal voltage generating circuit from each other in accordance with a control signal and connecting the internal voltage transmission line to a pad; and a buffer circuit coupled to the pad and made inactive in response to the control signal.
By monitoring the internal voltage externally and forcedly setting the voltage level of the internal voltage externally via the pad to which the buffer circuit is coupled and which is used in a normal use, the internal voltage can be monitored and forcedly applied without increasing the number of external pin terminals.
By selectively reading or forcedly setting a plurality of internal voltages via a single pad, the plurality of internal voltages can be monitored and forcedly set externally by using the minimum number of pin terminals.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.